加分成功

module top;
wire a,b,c,d;
wire f;

system_clock #400 clock1(a);
system_clock #200 clock2(b);
system_clock #100 clock3(c);
system_clock #50 clock4(d);

AOI_Unit m1(f,a,b,c,d);

endmodule

module AOI_Unit(f,a,b,c,d);
input a,b,c,d;
output f;
wire f1,f2,f3,f4,f5,a_bar,c_bar,b_bar,d_bar;
not #1(a_bar,a);
not #1(b_bar,b);
not #1(c_bar,c);
not #1(d_bar,d);
and #1(f1,a_bar,b_bar,d);
and #1(f2,b_bar,c_bar,d);
and #1(f3,a_bar,b,d_bar);
and #1(f4,a,c_bar,d_bar);
and #1(f5,a,b,c,d);
or #1(f,f1,f2,f3,f4,f5);
endmodule

module system_clock(clk);
parameter PERIOD = 100;
output　clk;
reg clk;
initial
　　clk = 0;
always begin#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule